Following are the details: : Start signal SCL High SDA High to Low
The Start signal appears at High to Low transition on the SDA line when SCL is High. : Write Slave Address The Write Slave Address is 70h or 72h. : Read Slave Address The Read Slave Address is 71h or 73h. : Value of the AL700/710 register index. : Acknowledge stage The host (master) generates acknowledge-related clock pulse. During the acknowledge clock pulse, the host must release the SDA line (to High) in order that AL700/701/710 (slave) can pull down the SDA. (c)2001,2002-Copyright by AverLogic Technologies, Corp. Preliminary Version C1.1 15
AL700/701/710
: Non-Acknowledged stage The host (master) generates acknowledge-related clock pulse. The host also releases the SDA line (to High) during the acknowledge clock pulse, but the AL700/701/710 does not pull it down during this stage. : Data byte written to or read from the register index In read operation, the host must release the SDA line (to High) before the first clock pulse is transmitted to the AL700/701/710.

: Stop signal SCL High SDA Low to High
The Stop signal appears at Low to High transition on the SDA line when SCL is High. Suppose data F0h is to be written to register 0Fh using write slave address 70h, the timing is as follows:
Start Slave a ddr = 70h Ack Ind ex = 0Fh Ack Data = F0h Ack Stop
SDA S CL
Figure 3: I2C Serial Bus Write Timing Suppose data is to be read from register 55h using read slave address 71h, the timing is as follows:
Start Slave a ddr = 70h Ack Ind ex = 55h Ack R e a d slave a ddr = 71h NAck Ack Data re a d cycle Stop Start
SDA S CL
Figure 4: I2C Serial Bus Read Timing
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
16
AL700/701/710
7.3.2 Proprietary Parallel Interface The parallel bus interface consists of the H_WRB (latch clock), H_BUS[7:0], H_DENB and H_RDB signals. There are internal pull-up circuits for all pins. When SP_SEL is high, the parallel bus interface is disabled and all parallel interface pins are pulled high. The parallel interface transfers base register address or read/write data in one H_WRB cycle. H_WRB is a latch clock signal. H_BUS[7:0] represents an 8-bit data bus. H_DENB defines the data bus as register address bus or data bus. The H_BUS[7:0] appears a register address at the rising edge of H_WRB when H_DENB is High. H_RDB defines Read/Write mode. The High H_RDB represents the host operates in the Write mode. At the rising edge of H_WRB, read/write data is latched or read-out data is read. The following figures show read/write timing chart of host parallel interface.
H_WRB HIZ
H_BUS(7:0) H_DENB ADDRESS READ H_RDB
address
DATA WRITE
Figure 5: Host Read Cycle
H_WRB
H_BUS(7:0) H_DENB ADDRESS WRITE H_RDB
address
data
don't care DATA
data
READ
Figure 6: Host Write Cycle 7.4 Picture Control AL700/701/710 provides various functions that can be controlled by inside registers. Picture control takes effect on the fly. Display attributes apply to all channels but channel attributes apply to each channel. 7.4.1 Picture Attributes AL700/701/710 provides QUAD or FULL screen picture display. In addition, picture location, layer priority and channel attributes can be programmed via host interface.
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
17
AL700/701/710
A C
B A D
Full Screen
QUAD Screen
Figure 7: QUAD and Full Screen Display Each channel can be located in any one position of left-top, left-bottom, right-top, and right-bottom screen in PIP (Picture In Picture) display mode. AL700/701/710 provides two-layer effect on picture layer priority. The bottom layer is always chosen as base video and the top layer shows the sub video window in PIP mode. These effects are defined by MTROUTSEL (#19h) and PIPCTRL (#1Ah) registers. LeftTop LeftBottom RightTop RightBottom
Bottom Layer Top Layer Picture Layer Priority
Picture Position
Figure 8: Picture Position and Picture Layer By setting up data in MTROUTSEL (#19h) and PIPCTRL (#1Ah) registers, you can get various useful features like PIP, channel overlay, sequential scan picture, anti-rolling switching channel, 1 to 4 picture display, and so on. 7.4.2 Display Attributes Display control will affect all channels at the same time. These controls include NTSC or PAL/SECAM system selection, background and full screen borderline color selection, and full screen borderline display/blink enable or disable. AL700/701/710 supports 525-line system in NTSC and 625-line system in PAL/SECAM. The Vsystem in SYSCONFIG register (#03h <0>) defines the video system. The background area is defined as outside of all active picture region. The background color is defined in BGColor (#20h <1:0>) and has four 24-bit color choices. The selected colors are defined in color Look Up Table (LUT). The full screen borderline color is defined in Border5_color (#14h <3:2>) and can be one of color 0, color 1, color 2, and color 3 defined in color LUT. No matter what channel is displayed in full screen, the full screen borderline color and blink attribute are the same. For the full screen display, it has its own control attributes to enable/disable or blink the (c)2001,2002-Copyright by AverLogic Technologies, Corp. Preliminary Version C1.1 18
AL700/701/710
borderline. The register Border5_enx (#14h <1:0>) is used to enable/disable full screen borderline in monitor output, VCR output, or both monitor and VCR outputs. The register Border5_blink (#15h <4>) controls the disable or enable of full screen borderline blink function.
A C
B A D
Full Screen
QUAD Screen
Figure 9: Borderline and Background Attributes 7.4.3 Channel Attributes There are independent channel configuration registers for each channel that can do various display control. The attribute controls include channel borderline enable or disable, channel borderline color, channel borderline blinking enable or disable, channel layer priority, channel location, channel image mirror enable or disable, and channel freeze control. The input channels are assigned to fixed locations of the four windows in QUAD screen display mode. In PIP mode, PIPCTRL (#1Ah) register controls each channel location. AL700/701/710 supports top and bottom layer priority that is only available in PIP mode. Base video channel defined by ChSel (#19h <1:0>) is always on the bottom layer. The sub video channel defined by PIPCTRL (#1Ah) is always on the top layer and enabled by LTPIP_en (#19h <4>), RTPIP_en (#19h <5>), LBPIP_en (#19h <6>), or RBPIP_en (#19h <7>). Each channel has its own borderline color and is defined in Border1_color (#10h <5:4>) for channel A, Border2_color (#11h <5:4>) for channel B, Border3_color (#12h <5:4>) for channel C, or Border4_color (#13h <5:4>) for channel D. The borderline color can be one of color 0, color 1, color 2, and color 3 defined in color LUT. Each channel also has its own enable or disable borderline display or blink controls. Border1_enx (#10h <3:2>), Border2_enx (#11h <3:2>), Border3_enx (#12h <3:2>), and Border4_enx (#13h <3:2>) are used to disable channel borderline display, or enable channel borderline display in monitor output, VCR output, or both monitor and VCR outputs for channel A, B, C, and D, respectively. Border1_blink (#15h <0>), Border2_blink (#15h <1>), Border3_blink (#15h <2>), and Border4_blink (#15h <3>) control the disable or enable of channel A, B, C, and D borderline blink function, respectively. Borderline is at a fixed position for each channel except Border1 (the left-top channel borderline) and the effect of BorderCenter (#18h <3>). HZOOMSTART (#1Eh) and VZOOMSTART (#1Fh) registers can shift the Border1 to mark the zoomed area. BorderCenter can overlay the borderline in the center of screen and its effect is shown in Figure 10. (c)2001,2002-Copyright by AverLogic Technologies, Corp. Preliminary Version C1.1 19
AL700/701/710
BorderCenter = 0
BorderCenter = 1
Figure 10: The Effect of BorderCenter Setting The picture can be frozen independently through controlling v1FreezeSel (#10h <1:0>), v2FreezeSel (#11h <1:0>), v3FreezeSel (#12h <1:0>), or v4FreezeSel (#13h <1:0>). Freeze function supports to capture a frame image, an odd field image, or an even field image. The image mirroring is supported in each channel at X-axis (horizontal axis) direction. Setting v1_flipx (#10h <6>), v2_flipx (#11h <6>), v3_flipx (#12h <6>), and v4_flipx (#13h <6>) to 1 can enable the mirror function of channel A, B, C, and D, respectively. 7.5 Video Loss AL700/701/710 supports video loss detection in both QUAD and FULL screen display modes. This is a very useful function in monitoring emergency situations. If there is an interrupt event due to video loss condition and the corresponding mask is not set to 1, the INTR pin will be active. The video loss condition refers to the following input signals: VALID 0, VALID 1, HSYNC, VSYNC, VCLK, DI [7:0] and Htotal_range (#0Fh <7:4>). Each signal can be enabled to reflect the video loss condition. VLOSSSIG (#0Ch) register controls the signal enable or disable attribute and applies the controls to all the channels. When one or more of the status bits are set during the operation that indicates the corresponding channels lose the input video signals. 7.6 Motion Detection AL700/701/710 supports hardware and software motion detection function. The motion detection function is always applied in the QUAD screen image of VCR output. The QUAD screen image is divided into 16 equal-size windows. Each video channel is assigned 4 windows. For hardware motion detection, each window in the same channel shares the same threshold of mean and variance defined in registers #70h~#7Fh. The motion detection algorithm built in AL700/701/710 uses the threshold of mean and variance to automatically (c)2001,2002-Copyright by AverLogic Technologies, Corp. Preliminary Version C1.1 20
AL700/701/710
detect an object motion. Once AL700/701/710 detects motion from any channel, the corresponding interrupt status (MotionA~D, #06h <7:4>) will reflect the incident. If the corresponding mask bit (Mask_MA~D, #07h<7:4>) is not set to 1, then the INTR pin will be active.
Window 0
Window 1
Window 2
Window 3
(Channel A)
Window 4 Window 5
(Channel B)
Window 6 Window 7
Window 8
Window 9
Window 10
Window 11
(Channel C)
Window 12 Window 13
(Channel D)
Window 14 Window 15
Figure 11: Motion-Detection Windows AL700/701/710 offers the calculating results, such as mean and variance, for each window, and system designers can implement their own motion detection algorithm based on these values. Through setting the window address of mean and variance (MOTIONADDR, #6Bh), one can read the mean data from MEANDATA registers (#6Ch and #6Dh), and the variance data from VARIANCEDATA registers (#6Eh and #6Fh). 7.7 2X Zoom AL700/701/710 provides 2X Zoom with interpolation function that allows you to watch a larger image twice the size of the original size in either real-time or frozen. This function applies an AverLogic proprietary interpolation algorithm to display a high quality image on the screen. When DisplayMode (#19h <3:2>) is set to ZOOM in mode, an area in each field defined by HzoomStart (#1Eh <6:0>) and VzoomStart (#01Fh <6:0>) will be zoomed in 2 times. The area size is 360x240 pixel-line in NTSC mode or 360x288 pixel-line in PAL mode. The unit of HzoomStart is 4 pixels and the unit of VzoomStart is 2 lines. Therefore, the horizontal left boundary (HLB) address equals to 4 times of HzoomStart and the vertical top boundary (VTB) address equals to 2 times of VzoomStart. (HLB, VTB) defines the original point of the zoomed in area. You can zoom in any 1/4 screen of base video image to full screen image as shown in figure 12. (c)2001,2002-Copyright by AverLogic Technologies, Corp. Preliminary Version C1.1 21
AL700/701/710
(HLB, VTB)
1/4 screen
Full screen
Figure 12: 2X Zoom In Function In application, Borderline 1 can be turned on first to preview the zooming area on QUAD or FULL display screen. The previewing window can be moved around by programming registers (HZOOMSTART, VZOOMSTART), and then change display to ZOOM in mode. 7.8 Overlay Control AL700/701/710 supports internal and external OSD (On-Screen Display) overlay control. By embedding SRAM, AL700/701/710 can overlay internal OSD text on top of the video for the applications like pop-up menu, message text or captions. Also AL700/701/710 can interface with external OSD chip. 7.8.1 Internal OSD mode There are 1K-byte Context RAM and 4K-byte Font RAM embedded to support internal OSD function. Two independent OSD (OSD1 and OSD2) windows are provided and can be enabled on monitor and/or VCR output respectively. If there is an overlap between OSD1 and OSD2, the OSD1 will be on the top display layer. The internal OSDs are very flexible in the way that the font, size, and display location are fully programmable. There are two kinds of OSD modes supported in the internal OSDs, they are 1-byte mode and 2-byte mode. The internal Context RAM storages the OSD character codes. The character codes in the Context RAM would be decoded as the index of the font table in Font RAM. Also included in the Context RAM is the blinking bit that can enable or disable the blinking function for the corresponding character. In 2-byte mode, additional attributes define the foreground and background color information related to the corresponding character. The OSD controller will generate OSD key after it reads out the font data. The OSD key selects the colors to be overlaid on the screen based on the data stored in Context RAM (in 2-byte mode) or the control registers (in 1-byte mode, #32h<3:0> and #42h<3:0>) that decide when and where these colors are displayed on the screen. The OSD key is used to select four out of 16 million (24 bits) OSD colors. The selected OSD characters and their color data are then passed through the internal blink control circuits. The blinking frequency is controlled by the BLINKCTRL (register #21h) with VYSNC as the reference counting clock. The blinking information is stored as data embedded with character codes stored in Context RAM.
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
22
AL700/701/710
After the processed blinking data is passed to the Boolean logic operation section, the Boolean logic operation section performs special OSD effects such as translucent, opaque, negative, and posterization. The Boolean logic operation feature, which provides a vivid and unique way of implementing display menu and status, is controlled by the FOREOP (#23h) register. The fading operation block creates the effect of smoothly fading in and fading out the OSD titles or menu. Fading is controlled by register ALPHA (#22h). Following is the block diagram of the AL700/701/710 OSD.
VIDEO DATA
RSTB CLK HSYNC VCNT HCNT OSD_CLK OSD_VBLK OSD_COLOR MONOSD_EN VCROSD_EN CONTEXT_RAMADDR CONTEXT_RAMDATA FONT_RAMADDR FONT_RAMDATA
C OLOR S ELE CT
BLINKING AND LOGIC O P ERATION
FADING O P ERATION
VIDEO+OSD
O SD CONTROL
OSDKEY
COLOR0 COLOR1 COLOR2 COLOR3
FOREOP
ALPHA
BLINK
OSD Registers setting
C ONTEXT_RAM 1K
FONT_RAM 4K
Figure 13: AL700/701/710 OSD Block Diagram The Context RAM is used to store the Character code or index for accessing a specific font (a font can be viewed as a pre-defined bitmap) stored in Font RAM. The address of the Character code is generated first to retrieve the index address to a specific font or bitmap. The following Font RAM address generators then calculate the address of the font stored in Font RAM based on the Character code read from Context RAM. The 8-bit data read from Font RAM is then unpacked into 1-bit or 2-bit data depending if 2-color mode or 4-color mode is selected. MSB bits are read out as OSD data before the LSB bits. This is illustrated as follows:
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
23
AL700/701/710
RAM Addre s s G e n erator 1 Font RAM Addre s s G e n erator 1
Context RAM ADDR 9
Context RAM
ContextRAM DATA 16
Font RAM ADDR 12
Font RAM 4K x 8
Font RAM DATA 8
OSDKEY Unp a cker 1/2
RAM Addre s s G e n erator 2
MUX
Font RAM Addre s s G e n erator 2
MUX
Figure 14: The Addressing of Context and Font RAMs The font addressing code can be in 1-byte or 2-byte formats. CONTEXTSTADDR1 (#36h) and CONTEXTSTADDR2 (#46h) are the starting addresses of the Character codes of OSD1 and OSD2 stored in Context RAM. The starting address should be an even number in the 2-byte data mode. The Character code is used to address the font data stored in Font RAM. The address of a data of a specific font is calculated as: Address = Font RAM Start Address + (Character code * Font Address Unit) + (OSD line count * FONTLINESIZE) The data format stored in Context RAM for addressing of OSD bitmap data is illustrated in the following diagram.
F o nt I n de x f or o ne b y t e da t a m o d e
00h Reserved<7> 01h Reserved<7> 02h Reserved<7> 03h Reserved<7> 04h Reserved<7> 05h Reserved<7> 06h Reserved<7>
1st Character code <6:0>
F o n t I n d ex f o r T w o b yt e d a t a m o d e
1st Character code <7:0> Foreground Color <7:6> Background Color <5:4> Blink <3> Character code <10:8>
00h
2nd Character code <6:0> 3rd Character code <6:0> 4th Character code <6:0>
01h 02h
Character code <7:0> Foreground Color <7:6> Background Color <5:4> Blink <3> Character code
5th Character code <6:0> 6th Character code <6:0> 7th Character code <6:0> 512th Character code <7:0> Foreground Color <7:6> Background Color <5:4> Blink <3> Character code
03h
3FEh 3FFh
Reserved<7> 1024th Character code <6:0>
3FFh
Figure 15: OSD Data Addressing in Context RAM 7.8.2 Internal OSD Timing The register OSDHSTART (#34h or #44h) refers to the horizontal starting position of the OSD window relative to the leading edge of HSYNC. OSDVSTART (#35h or #45h) refers to the vertical starting position of the OSD window relative to the leading edge of VSYNC. The BMAPHSIZE (#38h or #48h) defines the horizontal visible portion of the font (it can be smaller or equal to the actual horizontal font size). BMAPHTOTAL (#39h or #49h) is BMAPHSIZE plus the horizontal size of the border or gap in between fonts. The BMAPVSIZE (#3Ah or #4Ah) defines the vertical visible portion of the font (it can be smaller or equal to the actual vertical font size). BMAPVTOTAL (#3Bh or #4Bh) is (c)2001,2002-Copyright by AverLogic Technologies, Corp. Preliminary Version C1.1 24
AL700/701/710
BMAPVSIZE plus the vertical size of border or gap in between fonts. The total numbers of fonts in the horizontal and vertical directions are defined by ICONHTOTAL (#3Ch or #4Ch) and ICONVTOTAL (#3Dh or #4Dh). The screen-timing diagram of the OSD window is as follows:
HSYNC OSDHDE VSYNC OSDHDE
bmaphtotal Reg.# 39h,,49h osdhstart Reg.# 34h,44h
osdvstart Reg.# 35h,45h bmapvsize Reg.# 3Ah,4Ah bmapvtotal Reg.# 3Bh,4Bh
bmaphsize Reg.# 38h,48h
hgap
Row 1 Index 1
Row 1 Index 2
Row 1 Index 3
vgap
Row 2 Index 1
Row 2 Index 2
Row 2 Index 3
Row 3 Index 1
Row 3 Index 2
i c o nh t o t a l =3-1=2 Reg. # 3Ch,4Ch
background foreground
Figure 16: OSD Screen Timing Diagram 7.8.3 OSD Bitmap/Font Formatting The following two examples show how the bitmaps or fonts should be formatted for internal OSD operation. The first example uses 2-bit per pixel formatting:
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
i c on vt o t a l =3-1=2 Reg.# 3Dh,4Dh
25
AL700/701/710
Font line size = 5 bytes n+1<7:0>
7:6 5:4 3:2 1:0
n+2<7:0>
n+3<7:0>
n+4<7:0>
n<7:0> n+5<7:0> n+10<7:0> n+15<7:0>
0 3 3 3
000000000h C000003C0h C00000F00h C00003C00h
n+110<7:0>
n+111<7:0>
n+112<7:0>
n+113<7:0>
n+114<7:0>
n+115<7:0>
Bitmap horizontal size = 18 pixels
Figure 17: OSD Bitmap_Font Formating (2-bit per pixel) The next example uses 1-bit per pixel formatting:
Font line size = 3 bytes n+1<7:0>
7 6 5 4 3 2 1 0
n+2<7:0> 0 6 6 6 0 0 0 0 0 0 0 0 0 1 3 6 0 8 0 0 0 0 0 0 h h h h
n<7:0> n+3<7:0> n+6<7:0> n+9<7:0>
n+66<7:0> n+67<7:0> Bitmap horizontal size = 18 pixels n+68<7:0>
Figure 18: OSD Bitmap_Font Formating (1-bit per pixel)
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
26
AL700/701/710
7.8.4 External OSD Mode AL700/701/710 also supports external OSD mode. Most of the OSD devices use OSD_VBLK to define the OSD active region. AL700/701/710 uses MONOSD_EN and VCROSD_EN to decide whether the OSD Icons are shown on monitor and/or VCR display output. The OSD_COLOR selects the color from color 0 or color 1 defined in color LUT. The following diagram shows how the OSD_VBLK signal defines the OSD active region:
The example bellow describes the function of each OSD control signal.
7.9 Memory Interface AL700/701/710 supports various SDRAM configurations, such as 1Mx16 and 4Mx16 bit SDRAM, which can be selected by register #81h. AL700/701/710 uses sequential Burst mode to control SDRAM memory that operates at minimum 108MHz (9ns cycle time) of clock frequency. Also you can use DRAMCTL0 and DRAMCTL1 registers (#80h and #81h) to adjust the read/write performance of SDRAM. For detail operation of SDRAM, please reference memory maker specifications.
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
27
AL700/701/710
7.10 Image Data Upload AL700/701/710 supports 8-bit host bus that allows the microprocessor to directly read the digital image data from the SDRAM video memory. UPIMGCTR (#58h) register controls the image data uploading attributes. UPIMGYDP (#59h) and UPIMGCDP (#5Ah) registers store the Luminance and Chrominance data of a pixel, respectively. Internal image read counter will automatically increase when read UpImgYDP or UPImagCDP. To ensure image uploading correctly, the monitor output must be set to freeze mode and the internal image read counter must be reset before uploading an image. The pixel number of an image depends on the monitor display output mode. The first pixel is the upper most, top left point of a picture image. The image data is sequentially stored in the memory. The first pixel data of the following horizontal line is next to the last pixel data of the previous horizontal line. The microprocessor should calculate the image resolution, such as vertical and horizontal total pixels, to the read-out data so that it can re-build the picture image properly. 7.11 Interrupt AL700/701/710 interrupt function is supported by INTR pin, INTRSTATUS (#06h) and INTRMASK (#07h) registers. The Intr_pol (#03h <4>) controls the polarity of INTR pin. The INTR pin is active High if Intr_pol is set to 1 and vice versa. INTRSTATUS reflects the interrupt status of video loss or motion detection. Each bit of INTRSTATUS indicates one interrupt event and is active High. Set `1' to the corresponding bit in the INTRSTATUS register will clear the interrupt status. Each interrupt status bit has its mask bit to disable the hardware INTR signal. Set `1' to the corresponding bit in the INTRMASK register will prohibit that channel to activate the interrupt. The mask bit affects only the action of INTR and will not change the interrupt status in INTRSTATUS register. AL700/701/710 will issue an "INTR" request to an external micro-controller if there is at least one non-zero bit in the INTRSTATUS register and its corresponding mask bit is 0. 06h [7] 07h [7] [6] [5] [6] [5] INTRSTATUS [4] [3] [2] [1] R/W [0] R/W [2] [1] [0]
MotionD MotionC MotionB MotionA VdoLossD VdoLossC VdoLossB VdoLossA INTRMASK [4] [3]
Mask_MD Mask_MC Mask_MB Mask_MA Mask_VLD Mask_VLC Mask_VLB Mask_VLA
If INTR is active High, then using Boolean logic equation to express INTR is as follows: INTR = (MotionD AND Mask_MD) OR (MotionC AND Mask_MC) OR (MotionB AND Mask_MC) OR (MotionA AND Mask_MA) OR (VdoLossD AND Mask_VLD) OR (VdoLossC AND Mask_VLC) OR (VdoLossB AND Mask_VLB) OR (VdoLossA AND Mask_VLA) (c)2001,2002-Copyright by AverLogic Technologies, Corp. Preliminary Version C1.1 28
AL700/701/710
8 Register Definition
Registers are provided to setup AL700/701/710. These registers can be programmed via host interface. The host interface protocol is illustrated in "Host Interface" paragraph. The application notes will describe more detailed settings about these registers. Upon request, AverLogic will provide the sample code or tool of host interface control software. 8.1 Register Set Register Name Address System Configuration COMPANYID 00h REVISION 01h FAMILY 02h SYSCONFIG 03h DATAFORMAT 04h POLARITY 05h Interruption Status and Mask INTRSTATUS 06h INTRMASK 07h Capture Control CAPTURECTRL 08h CAPHSTART 09h, 0Ah CAPVSTART 0Bh VLOSSSIG 0Ch ADCTHRESHOLD 0Dh, 0Eh DECSWCTR 0Fh Channel Configuration CHACTRL 10h CHBCTRL 11h CHCCTRL 12h CHDCTRL 13h FULLBDRCTR 14h BDRBLINKCTR 15h 16h Display Control INTENCOUTSEL 17h DISPLAYCTRL 18h MTROUTSEL 19h PIPCTRL 1Ah DISPHSTART 1Bh, 1Ch DISPVSTART 1Dh HZOOMSTART 1Eh VZOOMSTART 1Fh R/W Default Function
R 46h Company ID R Revision number R 70/71h Chip family R/W 00h System configuration R/W 00h Input/Output data format R/W 00h Signal polarity R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Interruption status Interruption mask Capture control Horizontal capture start position Vertical capture start position Video loss referred Signal ADC threshold Decoder switch control Channel A control Channel B control Channel C control Channel D control Full border line control Border line blink control Reserved Internal encoder output selection Display control Monitor output configuration Picture in picture control Horizontal display start position Vertical display start position The left boundary of zoom-in area The top boundary of zoom-in area Preliminary Version C1.1 29
R/W R/W R/W R/W R/W R/W R/W R/W
00h 00h 00h 00h 00h 00h 00h 00h
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
AL700/701/710
Register Name Overlay Control OVERLAYCTRL BLINKCTRL ALPHA FOREOP LUT0Y LUT0U LUT0V LUT1Y LUT1U LUT1V LUT2Y LUT2U LUT2V LUT3Y LUT3U LUT3V OSD 1 Control OSDCONTROL1 FONTSTADDR1 FONTADDRUNIT1 FONTLINESIZE1 OSDHSTART1 OSDVSTART1 CONTEXTSTADDR1 RAMSTRIDE1 BMAPHSIZE1 BMAPHTOTAL1 BMAPVSIZE1 BMAPVTOTAL1 ICONHTOTAL1 ICONVTOTAL1 OSD 2 Control OSDCONTROL2 FONTSTADDR2 FONTADDRUNIT2 FONTLINESIZE2 OSDHSTART2 OSDVSTART2 CONTEXTSTADDR2 RAMSTRIDE2
Address R/W Default 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh, 3Fh 40h 41h 42h 43h 44h 45h 46h 47h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
Function Overlay control Blinking control Alpha register Overlay Boolean operation Look-up table (LUT) color 0 - Luminance Y LUT color 0 - Chrominance U LUT color 0 - Chrominance V LUT color 1 - Luminance Y LUT color 1 - Chrominance U LUT color 1 - Chrominance V LUT color 2 - Luminance Y LUT color 2 - Chrominance U LUT color 2 - Chrominance V LUT color 3 - Luminance Y LUT color 3 - Chrominance U LUT color 3 - Chrominance V OSD1 control OSD1 Font RAM start address OSD1 font address unit OSD1 font line size OSD1 horizontal start point OSD1 vertical start point OSD1 context RAM start address OSD1 RAM line stride OSD1 bitmap horizontal size OSD1 bitmap total horizontal size OSD1 bitmap vertical size OSD1 bitmap total vertical size OSD1 total horizontal icons OSD1 total vertical icons Reserved OSD2 control OSD2 Font RAM start address OSD2 font address unit OSD2 font line size OSD2 horizontal start point OSD2 vertical start point OSD2 context RAM start address OSD2 RAM line stride Preliminary Version C1.1 30
R/W R/W R/W R/W R/W R/W R/W R/W
00h 00h 00h 00h 00h 00h 00h 00h
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
AL700/701/710
Register Name BMAPHSIZE2 BMAPHTOTAL2 BMAPVSIZE2 BMAPVTOTAL2 ICONHTOTAL2 ICONVTOTAL2 RAM Access ADDRL ADDRM ADDRH DATAPORT Image Upload Setting UPIMGCTR UPIMGYDP UPIMGCDP
Address 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh, 4Fh 50h 51h 52h 53h 54~57h
R/W Default Function R/W 00h OSD2 bitmap horizontal size R/W 00h OSD2 bitmap total horizontal size R/W 00h OSD2 bitmap vertical size R/W 00h OSD2 bitmap total vertical size R/W 00h OSD2 total horizontal icons R/W 00h OSD2 total vertical icons Reserved W W W W 00h 00h 00h 00h Address [7:0] Address [15:8] Target selection & Address [17:16] Data port Reserved Upload image control Upload image Y read port Upload image C read port Reserved Output HSYNC width Output VSYNC width Reserved Mean and Variance address Data of mean Data of variance Threshold of mean 0 Threshold of mean 1 Threshold of mean 2 Threshold of mean 3 Threshold of variance 0 Threshold of variance 1 Threshold of variance 2 Threshold of variance 3 SDRAM timing parameters SDRAM enable control SDRAM minimum refresh control Channel A quad capture FIFO control Channel B quad capture FIFO control Channel C quad capture FIFO control Channel D quad capture FIFO control Preliminary Version C1.1 31
58h R/W 59h R 5Ah R 5B~5Fh External Encoder Interface Setting HSYNCWIDTH 60h, 61h R/W VSYNCWIDTH 62h R/W 63~6Ah Motion Detection MOTIONADDR 6Bh W MEANDATAL, H 6Ch, 6Dh R VARIANCEDATAL, H 6Eh, 6Fh R MEANTH0L, H 70h, 71h W MEANTH1L, H 72h, 73h W MEANTH2L, H 74h, 75h W MEANTH3L, H 76h, 77h W VARIANCETH0L, H 78h, 79h W VARIANCETH1L, H 7Ah, 7Bh W VARIANCETH2L, H 7Ch, 7Dh W VARIANCETH3L, H 7Eh, 7Fh W SDRAM Interface DRAMCTRL0, 1 80h, 81h R/W ENABLE_CTRL 82h R/W MIN_REFRESH 83h R/W CAW_LEVEL 84h R/W CBW_LEVEL 85h R/W CCW_LEVEL 86h R/W CDW_LEVEL 87h R/W
00h 00h 00h
00h 00h
00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 08h 08h 08h 08h
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
AL700/701/710
Register Name CFW_LEVEL QDR_LEVEL FDR_LEVEL Test Registers
Address 88h 89h 8Ah 8B~8Fh 90~9Fh
R/W Default Function R/W 10h Full video capture FIFO control R/W 10h VCR output display FIFO control R/W 10h Monitor output display FIFO control Reserved 00h Reserved for factory test only
8.2 Register Description 8.2.1 System Configuration 00h [7] [6] [5] COMPANYID [4] [3] [2] [1] CompanyId COMPANYID: Defines the company ID. CompanyId 01h [7] [6] [5] <7:0> Company ID (default value is 46h) REVISION [4] [3] [2] [1] Revision REVISION: Defines the IC revision number. Revision 02h [7] [6] [5] <7:0> Revision number FAMILY [4] Family FAMILY: Defines the chip family. Family <7:0> 0x70 AL700 series 0x71 AL710 series [3] [2] [1] R [0] R [0] R [0]
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
32
AL700/701/710
03h [7] [6] [5]
SYSCONFIG [4] [3] [2] [1] ITU-R601-16bit
R/W [0] Vsystem
disp_tstb cap_tstb dram_rstb Intr_pol Reserved OSDsource SYSCONFIG: Defines the system configurations. Vsystem <0> 0 1 ITU-R-601_16bit <1> 0 1 OSDsource <2> 0 1 Intr_pol <4> 0 1 dram_rstb <5> 0 1 cap_rstb <6> 0 1 disp_rstb <7> 0 1
Video system (default value is 0) 525 line system (like as NTSC) 625 line system (like as PAL/SECAM) Bus width of ITU-R-601 output data (default value is 0) 8 bits 16 bits (suitable for AL250/251) Select OSD source (default value is 0) Use internal OSD controller Use external OSD IC Defines interrupt active level (default value is 0) Interrupt active Low Interrupt active High Used to reset the SDRAM interface (default value is 0) Normal Reset SDRAM interface Used to rest capture interface (default value is 0) Normal Reset capture interface Used to reset display interface (default value is 0) Normal Reset display interface
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
33
AL700/701/710
04h [7] Reserved [6] [5] OutSeq
DATAFORMAT [4] Out656 [3] Rev_Vclk_en [2] InSeq [1]
R/W [0] In656
DATAFORMAT: Defines the input/output data formats. In656 <0> 0 Enable ITU-R-656 format for input data (default value is 0) ITU-R-601 compatible 4:2:2 YCrCb video format with independent sync and flag signals. AL710 only supports ITU-R-601 format. ITU-R-656 compatible video format with embedded sync signal Select YCrCb sequence for input data (default value is 00) Cb, Y, Cr, Y Cr, Y, Cb, Y Y, Cb, Y, Cr Y, Cr, Y, Cb Select video clock output pattern (default value is 0) Normal Reverse video clock output (VCLK) Enable ITU-R-656 format for output data (default value is 0) ITU-R-601 compatible 4:2:2 YCrCb video format with independent sync and flag signals. AL710 only supports ITU-R-601 format. ITU-R-656 compatible video format with embedded sync signal Select YCrCb sequence for output data (default value is 00) Cb, Y, Cr, Y Cr, Y, Cb, Y Y, Cb, Y, Cr Y, Cr, Y, Cb
1 InSeq <2:1> 00 01 10 11 Rev_Vclk_en <3> 0 1 Out656 <4> 0
1 OutSeq <6:5> 00 01 10 11
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
34
AL700/701/710
05h [7] [6] [5]
POLARITY [4] [3] [2] [1] InHsPol
R/W [0] InVsPol
Reserved field_det OutFldPol OutHsPol OutVspol InFldPol POLARITY: Defines the signal polarity. InVsPol <0> 0 1 InHsPol <1> 0 1 InFldPol <2> 0 1 OutVsPol <3> 0 1 OutHsPol <4> 0 1 OutFldPol <5> 0 1 field_det <6> 0 1
Choose input vertical sync polarity (default value is 0) Positive polarity Negative polarity Choose input horizontal sync polarity (default value is 0) Positive polarity Negative polarity Choose input field polarity (default value is 0) Positive polarity Negative polarity Choose output vertical sync polarity (default value is 0) Positive polarity Negative polarity Choose output horizontal sync polarity (default value is 0) Positive polarity Negative polarity Choose output field polarity (default value is 0) Positive polarity Negative polarity Choose field detection mode (default value is 0) Use external signal Detected by Horizontal sync and Vertical sync
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
35
AL700/701/710
8.2.2 Interruption Status and Mask 06h [7] [6] [5] INTRSTATUS [4] [3] [2] [1] R/W [0]
MotionD MotionC MotionB MotionA VdoLossD VdoLossC VdoLossB VdoLossA INTRSTATUS: Defines the interrupt status. There indicates a corresponding interrupt while reading `1' at a bit. Write `1' to a bit will clear the corresponding interrupt status. There is no effect while writing `0' to any bit. Default value is 0. VdoLossA VdoLossB VdoLossC VdoLossD MotionA MotionB MotionC MotionD 07h [7] [6] [5] <0> <1> <2> <3> <4> <5> <6> <7> Status of video loss from channel A Status of video loss from channel B Status of video loss from channel C Status of video loss from channel D Status of motion detection from channel A Status of motion detection from channel B Status of motion detection from channel C Status of motion detection from channel D INTRMASK [4] [3] [2] [1] R/W [0]
Mask_MD Mask_MC Mask_MB Mask_MA Mask_VLD Mask_VLC Mask_VLB Mask_VLA
INTRMASK: Defines the interrupt masks. There represents that a corresponding interrupt is masked while writing `1' to a bit. AL700/701/710 will issue an "INTR" request to an external micro-controller if there is at least one non-zero bit in the INTRSTATUS register and its corresponding mask bit is 0. Default value is 0. Mask_VLA Mask_VLB Mask_VLC Mask_VLD Mask_MA Mask_MB Mask_MC Mask_MD <0> <1> <2> <3> <4> <5> <6> <7> Mask of video loss from channel A Mask of video loss from channel B Mask of video loss from channel C Mask of video loss from channel D Mask of motion detection from channel A Mask of motion detection from channel B Mask of motion detection from channel C Mask of motion detection from channel D Preliminary Version C1.1 36
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
AL700/701/710
8.2.3 Capture Control 08h [7] [6] [5] CAPTURECTRL [4] [3] [2] [1] R/W [0]
ext_syncsep Field_Cap Samplerate mux_mode Reserved SoftRef Qualify1 Qualify0 _sel CAPTURECTRL: Defines the capture control features. Qualify0 <0> 0 1 Qualify1 <1> 0 1 SoftRef <2> Select operation for qualified data (default value is 0) Choose valid 0 for each channel Choose the reverse of valid 0 for each channel (~valid 0) Select operation for qualified data (default value is 0) Choose valid 1 for each channel Choose reverse of valid 1 for each channel (~valid 1) Select data-valid modes. Default value is 0. For AL710, this bit should be set to `1' and the registers 09h, 0Ah, and 0Bh should be set appropriate values. Valid data is qualified by the hardware valid pins in ITU-R-601 mode or HACTIVE code in ITU-R-656 mode Capture start is defined by registers 09h, 0Ah, and 0Bh Choose the number of decoders (default value is 0) normal (connect 4 external decoders) 1 decoder for 2 channels (connect 2 external decoders) Select ADC sample rate (only for AL710, default value is 0) 27 MHz 54 MHz Choose field capture mode (default value is 0) Capture odd field only Capture maybe either odd or even field Defines sync separator source (only for AL710, default value is 1)
0
1 mux_mode <4> 0 1 Samplerate_sel <5> 0 1 Field_Cap <6> 0 1 ext_syncsep <7>
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
37
AL700/701/710
0
Use internal sync separator for AL710. Not only the Samplerate_sel bit but also the registers 0Dh and 0Eh should be set appropriate values. The decoder input pins used in this mode are DI_A[7:0], DI_B[7:0], DI_C[7:0], DI_D[7:0], VCLK_A, VCLK_B, VCLK_C, and VCLK_D. Use external sync separator for AL710 CAPHSTART R/W [2] [1] [0] R/W [2] [1] [0] CapHStart[9:8]
1 09h [7] 0Ah [7] [6] [5] [6] [5]
[4]
[3]
CapHStart[7:0] CAPHSTART [4] [3] Reserved
CAPHSTART: Defines the horizontal capture start position. Default value is 0. The unit is one pixel. CapHStart[7:0] CapHStart[9:8] 0Bh [7] [6] [5] <7:0> <1:0> Bits<7:0> of horizontal capture start position Bits<9:8> of horizontal capture start position CAPVSTART [4] [3] [2] [1] CapVStart[7:0] CAPVSTART: Defines the vertical capture start position. Default value is 0. The unit is one line. CapVStart 0Ch [7] [6] [5] <7:0> Vertical capture start position VLOSSSIG [4] [3] [2] [1] R/W [0] R/W [0]
DATA_Loss CLK_Loss Htotal_Loss VS_Loss HS_Loss Reserved Val1_Loss Val0_Loss VLOSSSIG: Enables the video loss referred signals. Default value is 0. There represents that the signal is enabled if the corresponding bit is set to `1'. The Vloss will be enabled if there is any one bit enabled. Val0_Loss <0> 0 1 Val1_Loss <1> Enable the Valid 0 loss signal Disable Enable Enable the Valid 1 loss signal Preliminary Version C1.1 38
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
AL700/701/710
0 1 Reserved HS_Loss <2> <3> 0 1 VS_Loss <4> 0 1 Htotal_Loss <5> 0 1 CLK_Loss <6> 0 1 DATA_Loss <7> 0 1
Disable Enable Reserved Enable the horizontal sync loss signal Disable Enable Enable the vertical sync loss signal Disable Enable Enable the horizontal total pixel loss signal Disable Enable Enable the clock loss signal Disable Enable Enable the data loss signal Disable Enable
Vloss = Val0_Loss or Val1_Loss or HS_Loss or VS_Loss or Htotal_Loss or CLK_Loss or DATA_Loss 0Dh [7] 0Eh [7] [6] [5] ADC4_Threshold [6] [5] ADC2_Threshold ADCTHRESHOLD [4] [3] [2] [1] ADC3_Threshold ADCTHRESHOLD [4] [3] [2] [1] ADC1_Threshold R/W [0] R/W [0]
ADCTHRESHOLD: Defines the threshold of ADC. Default values are 0. These registers are only available for AL710. The unit is the same as the external ADC resolution. ADC1_Threshold ADC2_Threshold ADC3_Threshold <3:0> <3:0> ADC threshold of channel A ADC threshold of channel C Preliminary Version C1.1 39 <7:4> ADC threshold of channel B
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
AL700/701/710
ADC4_Threshold 0Fh [7] [6]
<7:4>
ADC threshold of channel D DECSWCTR R/W [2] [1] [0] Swithc_Dly
[5]
[4]
[3]
Htotal_range
DECSWCTR: Defines the delayed field numbers while switching channel and the horizontal total lost pixels during two Hsync signals for video loss detection. Switch_Dly Htotal_range <3:0> <7:4> Field numbers delayed while switching channel (default value is 0) Horizontal total pixel range for video loss detection (default value is 0)
8.2.4 Channel Configuration 10h [7] Reserved 11h [7] Reserved 12h [7] Reserved 13h [7] Reserved [6] V4_flipx [5] [6] V3_flipx [5] [6] V2_flipx [5] [6] V1_flipx [5] CHACTRL [4] [3] [2] [1] Border1_color [4] Border1_enx [3] [2] R/W [0] R/W [1] [0] R/W [2] [1] [0] R/W [2] [1] [0] v4FreezeSel v3FreezeSel v2FreezeSel v1FreezeSel
CHBCTRL Border2_color [4] Border2_enx [3]
CHCCTRL Border3_color [4] Border3_enx [3]
CHDCTRL Border4_color Border4_enx
CHACTRL, CHBCTRL, CHCCTRL, CHDCTRL: Defines the control configurations of channel A, B, C, and D repectively. v1FreezeSel v2FreezeSel v3FreezeSel v4FreezeSel Border1_enx <1:0> 00 01 10 11 <3:2> Select freeze mode (default value is 0) Normal (live video) Freeze a frame image Freeze an odd field image Freeze an even field image Control borderline display (default value is 0) Preliminary Version C1.1 40
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
AL700/701/710
Border2_enx Border3_enx Border4_enx Border1_color Border2_color Border3_color Border4_color v1_flipx v2_flipx v3_flipx v4_flipx 14h [7] [6]
00 01 10 11 <5:4> 00 01 10 11 <6> 0 1
Disable Enable monitor Enable VCR Enable both monitor and VCR Select borderline color (default value is 0) LUT 0 LUT 1 LUT 2 LUT 3 Mirror the channel video image at X-axis (default value is 0) Normal (no mirror) Enable mirror function FULLBDCTRL R/W [2] [1] [0] Border5_enx
[5]
[4]
[3]
Reserved
Border5_color
FULLBDRCTR: Defines the control configurations of full borderline. Border5_enx <1:0> 00 01 10 11 Border5_color <3:2> 00 01 10 11 Control borderline display (default value is 0) Disable Enable monitor Enable VCR Enable both monitor and VCR Select borderline color (default value is 0) LUT 0 LUT 1 LUT 2 LUT 3
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
41
AL700/701/710
15h [7] [6] Reserved [5]
BDRBLINKCTR [4] [3] [2] [1]
R/W [0]
Border5_ Border4_ Border3_ Border2_ Border1_ blink blink blink blink blink
BDRBLINKCTR: Defines the borderline blink controls. Border1_blink <0> 0 1 Border2_blink <1> 0 1 Border3_blink <2> 0 1 Border4_blink <3> 0 1 Border5_blink <4> 0 1 8.2.5 Display Control 17h [7] [6] [5] Reserved INTENCOUTSEL [4] [3] [2] [1] RevVCRField RevMonField R/W [0] Ienc_Out_Sel Enable Border1 blink function (default value is 0) Normal (on blink) Blink Enable Border2 blink function (default value is 0) Normal (on blink) Blink Enable Border3 blink function (default value is 0) Normal (on blink) Blink Enable Border4 blink function (default value is 0) Normal (on blink) Blink Enable Border5 blink function (default value is 0) Normal (on blink) Blink
INTENCOUTSEL: Selects internal encoder outputs and field polarity. Ienc_Out_Sel <1:0> 00 01 10 Choose the output formats for monitor and VCR (default value is 0) Composite output for both monitor and VCR S-video output for monitor and Composite output for VCR Composite output for monitor and S-video output for VCR Preliminary Version C1.1 42
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
AL700/701/710
11 RevMonField <2> 0 1 RevVCRField <3> 0 1 18h [7] [6] [5]
Reserved Reverse the field polarity of monitor output (default value is 0) Normal Reverse Reverse the field polarity of VCR output (default value is 0) Normal Reverse DISPLAYCTRL [4] [3] [2] [1] R/W [0]
Genlock Reserved ColorBar BW BorderCenter BorderWidth Enc_clksel EncoderSel DISPLAYCTRL: Defines the control configurations of display. EncoderSel <0> 0 1 Enc_clksel <1> 0 1 BorderWidth <2> 0 1 BorderCenter <3> 0 1 BW <4> 0 1 ColorBar <5> Select encoder source (default value is 0) Use internal encoders Use external encoders Select internal encoder clock (default value is 0) 4 times of video clock frequency (14.3182MHz for NTSC, 17.7345MHz for PAL) 27 MHz Select borderline width (default value is 0) 4 pixels 8 pixels Choose the overlay width of borderline (default value is 0) Normal (no overlay) overlay the borderlines in the center of screen Enable black and white mode of video output (only for AL700/701, default value is 0) Normal Video output is black and white Generate Color-Bar pattern (default value is 0) Preliminary Version C1.1 43
Note: For AL701, this bit should be set to "1".
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
AL700/701/710
0 1 Genlock <7>
Display normal picture Display Color-Bar Pattern Select the source of Sync timing for external encoder (default value is 0 and only valid when EncorderSel is set to 1) Use internally generated sync timing Sync timing generated by external encoder MTROUTSEL R/W [2] [1] ChSel [0]
0 1 19h [7] [6] [5]
[4]
[3]
RBPIP_en LBPIP_en RTPIP_en LTPIP_en
DisplayMode
MTROUTSEL: Defines the configurations of monitor output. ChSel <1:0> 00 01 10 11 DisplayMode <3:2> 00 01 10 11 LTPIP_en <4> 0 1 RTPIP_en <5> 0 1 LBPIP_en <6> 0 Choose a channel as base video in FULL, PIP, or ZOOM mode (default value is 0) Choose channel A Choose channel B Choose channel C Choose channel D Select display mode (default value is 0) QUAD mode FULL mode PIP mode (Picture In Picture) ZOOM in mode Enable the Left-Top window to show sub video in PIP mode (default value is 0) Disable Enable Enable the Right-Top window to show sub video in PIP mode (default value is 0) Disable Enable Enable the Left-Bottom window to show sub video in PIP mode (default value is 0) Disable Preliminary Version C1.1 44
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
AL700/701/710
1 RBPIP_en <7> 0 1 1Ah [7] [6] [5] RB_ChSel
Enable Enable the Right-Bottom window to show sub video in PIP mode (default value is 0) Disable Enable PIPCTRL [4] [3] [2] [1] LB_ChSel RT_ChSel R/W [0] LT_ChSel
PIPCTRL: Defines video channel source for each display window in PIP display mode. LT_ChSel <1:0> 00 01 10 11 RT_ChSel <3:2> 00 01 10 11 LB_ChSel <5:4> 00 01 10 11 RB_ChSel <7:6> 00 01 10 11 Choose video channel for Left-Top window in PIP display mode (default value is 0) Choose channel A Choose channel B Choose channel C Choose channel D Choose video channel for Right-Top window in PIP display mode (default value is 0) Choose channel A Choose channel B Choose channel C Choose channel D Choose video channel for Left-Bottom window in PIP display mode (default value is 0) Choose channel A Choose channel B Choose channel C Choose channel D Choose video channel for Right-Bottom window in PIP display mode (default value is 0) Choose channel A Choose channel B Choose channel C Choose channel D Preliminary Version C1.1 45
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
AL700/701/710
1Bh [7] 1Ch [7] [6] [5] [6] [5]
DISPHSTART [4] [3] [2] [1] DispHStart[7:0] DISPHSTART [4] [3] [2] [1] Reserved
R/W [0] R/W [0] DispHStart[9:8]
DISPHSTART: Defines the horizontal display start position. Default value is 0. The unit is 2 pixels. DispHStart[7:0] DispHStart[9:8] 1Dh [7] [6] [5] <7:0> <1:0> Bits<7:0> of horizontal display start position Bits<9:8> of horizontal display start position DISPVSTART [4] [3] [2] [1] DispVStart[7:0] DISPVSTART: Defines the vertical display start position. Default value is 0. The unit is 2 lines. DispVStart 1Eh [7] Reserved [6] [5] <7:0> Bits<7:0> of vertical display start position HZOOMSTART [4] [3] HZoomStart[6:0] [2] [1] R/W [0] R/W [0]
HZOOMSTART: Defines the left boundary of ZOOM in area. Default value is 0. The unit is 4 pixels. HZoomStart <6:0> Define the position of left boundary Horizontal left boundary (HLB) = HZoomStart * 4 pixels Horizontal right boundary = HLB + 360 pixels The value of HZoomStart must be less than 0x5A. 1Fh [7] Reserved [6] [5] VZOOMSTART [4] [3] VZoomStart[6:0] [2] [1] R/W [0]
VZOOMSTART: Defines the top boundary of ZOOM in area. Default value is 0. The unit is 2 lines. VZoomStart <6:0> Define the position of top boundary Preliminary Version C1.1 46
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
AL700/701/710
Vertical top boundary (VTB) = VZoomStart * 2 lines Vertical bottom boundary = VTB + 240 lines (for NTSC) or = VTB + 288 lines ( for PAL) The value of VzoomStart must be less than 0x78 for NTSC system and 0x90 for PAL system. When DisplayMode is set to ZOOM in mode, an area in each field defined by HzoomStart and VzoomStart will be zoomed in 2 times. The area size is 360x240 pixel-line in NTSC mode or 360x288 pixel-line in PAL mode. (HLB, VTB) defines the original point of the zoomed in area. 8.2.6 Overlay Control 20h [7] [6] [5] OVERLAYCTRL [4] [3] [2] [1] Reserved OVERLAYCTRL: Defines the control configurations of overlay. BGColor <1:0> 00 01 10 11 21h [7] [6] [5] Reserved Choose background color (default value is 0) Choose color 0 in color LUT Choose color 1 in color LUT Choose color 2 in color LUT Choose color 3 in color LUT BLINKCTRL [4] [3] [2] [1] BlinkType R/W [0] BlinkTime R/W [0] BGColor
BLINKCTRL: Defines the control configurations of blink. BlinkTime <1:0> 00 01 10 11 BlinkType <3:2> 00 01 10 11 Set the blinking time constant (default value is 0) 32 frames of internal reference timing per blink 64 frames of internal reference timing per blink 128 frames of internal reference timing per blink 256 frames of internal reference timing per blink Choose blinking type (default value is 0) Blinking is defined by BlinkTime No blinking, just reverse the index color By pass Reserved Preliminary Version C1.1 47
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
AL700/701/710
22h [7] [6] [5] Reserved
ALPHA [4] [3] Alpha[5:0] [2] [1]
R/W [0]
ALPHA: Defines the factor for fading effect. Default value is 0. Alpha <5:0> The range of value is from 00h to 20h, that is, there are 33 levels of fade-in/fade-out effects. output = input * + overlay * (1-(/32)) 23h [7] [6] [5] Color3Op Color2Op FOREOP [4] [3] [2] [1] Color1Op R/W [0] Color0Op
FOREOP: Defines the overlay Boolean logic operations. Color0Op <1:0> 00 01 10 11 Color1Op <3:2> 00 01 10 11 Color2Op <5:4> 00 01 Select the Boolean logic operation between color 0 and video (default value is 0) NOP operation: shows OSD bitmap image only OR operation: displays the image after executing the OR Boolean logic operation of video and color 0 AND operation: displays the image after executing the AND Boolean logic operation of video and color 0 XOR operation: displays the image after executing the XOR Boolean logic operation of video and color 0 Select the Boolean logic operation between color 1 and video (default value is 0) NOP operation: shows OSD bitmap image only OR operation: displays the image after executing the OR Boolean logic operation of video and color 1 AND operation: displays the image after executing the AND Boolean logic operation of video and color 1 XOR operation: displays the image after executing the XOR Boolean logic operation of video and color 1 Select the Boolean logic operation between color 2 and video (default value is 0) NOP operation: shows OSD bitmap image only OR operation: displays the image after executing the OR Boolean logic operation of video and color 2 Preliminary Version C1.1 48
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
AL700/701/710
10 11 Color3Op <7:6> 00 01 10 11
AND operation: displays the image after executing the AND Boolean logic operation of video and color 2 XOR operation: displays the image after executing the XOR Boolean logic operation of video and color 2 Select the Boolean logic operation between color 3 and video (default value is 0) NOP operation: shows OSD bitmap image only OR operation: displays the image after executing the OR Boolean logic operation of video and color 3 AND operation: displays the image after executing the AND Boolean logic operation of video and color 3 XOR operation: displays the image after executing the XOR Boolean logic operation of video and color 3 LUT0Y W [3] LUT0U [2] [1] [0] W [3] LUT0V [2] [1] [0] W [3] [2] [1] [0]
24h [7] 25h [7] 26h [7] [6] [5] [4] [6] [5] [4] [6] [5] [4]
LUT0Y[7:0]
LUT0U[7:0]
LUT0V[7:0] LUT0Y, LUT0U, LUT0V: Defines the Color 0 of Look-up Table (LUT). Default value is 0. LUT0Y LUT0U LUT0V <7:0> <7:0> <7:0> Define the Y Luminance of color 0 in LUT Define the U Chrominance of color 0 in LUT Define the V Chrominance of color 0 in LUT
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
49
AL700/701/710
27h [7] 28h [7] 29h [7] [6] [5] [4] [6] [5] [4] [6] [5] [4]
LUT1Y [3] LUT0U [3] LUT0V [3] [2] [1] LUT1V[7:0] [2] [1] LUT1U[7:0] [2] [1] LUT1Y[7:0]
W [0] W [0] W [0]
LUT1Y, LUT1U, LUT1V: Defines the Color 1 of Look-up Table (LUT). Default value is 0. LUT1Y LUT1U LUT1V 2Ah [7] 2Bh [7] 2Ch [7] [6] [5] [4] [6] [5] [4] LUT2V [3] [2] [1] LUT2V[7:0] LUT2Y, LUT2U, LUT2V: Defines the Color 2 of Look-up Table (LUT). Default value is 0. LUT2Y LUT2U LUT2V <7:0> <7:0> <7:0> Define the Y Luminance of color 2 in LUT Define the U Chrominance of color 2 in LUT Define the V Chrominance of color 2 in LUT [6] [5] [4] LUT2U [3] [2] [1] LUT2U[7:0] W [0] <7:0> <7:0> <7:0> Define the Y Luminance of color 1 in LUT Define the U Chrominance of color 1 in LUT Define the V Chrominance of color 1 in LUT LUT2Y [3] [2] [1] LUT2Y[7:0] W [0] W [0]
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
50
AL700/701/710
2Dh [7] 2Eh [7] 2Fh [7] [6] [5] [4] [6] [5] [4] [6] [5] [4]
LUT3Y [3] LUT3U [3] LUT3V [3] [2] [1] LUT3V[7:0] [2] [1] LUT3U[7:0] [2] [1] LUT3Y[7:0]
W [0] W [0] W [0]
LUT3Y, LUT3U, LUT3V: Defines the Color 3 of Look-up Table (LUT). Default value is 0. LUT3Y LUT3U LUT3V 8.2.7 OSD1 Control 30h [7] OSD1Blink_en [6] [5] OsdEn1 OSDCONTROL1 [4] Font2Byte1 [3] [2] [1] Vzoom1 R/W [0] Hzoom1 <7:0> <7:0> <7:0> Define the Y Luminance of color 3 in LUT Define the U Chrominance of color 3 in LUT Define the V Chrominance of color 3 in LUT
OSDCONTROL1: Defines the control configurations of OSD1 (On Screen Display 1) Hzoom1 <1:0> 00 01 10 11 Vzoom1 <3:2> 00 01 10 11 Select the horizontal zoom factor of OSD 1 (default value is 0) OSD horizontal pixel size = 1 times of video pixel OSD horizontal pixel size = 2 times of video pixel OSD horizontal pixel size = 4 times of video pixel OSD horizontal pixel size = 8 times of video pixel Select the vertical zoom factor of OSD 1 (default value is 0) OSD vertical pixel size = 2 times of video pixel OSD vertical pixel size = 4 times of video pixel OSD vertical pixel size = 8 times of video pixel OSD vertical pixel size = 16 times of video pixel Preliminary Version C1.1 51
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
AL700/701/710
Font2Byte1
<4> 0 1
Select font character code mode (default value is 0) One-byte character code mode Two-byte character code mode OSD1 output selection (default value is 0) Disable OSD1 Enable OSD1 in monitor output Enable OSD1 in VCR output Enable OSD1 in both monitor and VCR output Enable OSD1 blink function (default value is 0) Disable OSD1 blink Enable OSD1 blink
OsdEn1
<6:5> 00 01 10 11
OSD1Blink_en
<7> 0 1
The blink attribute in the Context RAM will be disabled if the OSD1Blink_en is set to 0. 31h [7] [6] [5] FONTSTADDR1 [4] [3] [2] [1] FontStAddr1[7:0] FONTSTADDR1: Defines the start address of OSD 1 Font RAM. Default value is 0. FontStAddr1 <7:0> OSD1 Font RAM start address (Unit: 8 bytes) OSD1 Font RAM start address = FontStAddr1 * 8 There is 4K Byte Font RAM built in AL700/701/710. 32h [7] PixelDepth1 [6] [5] FontAddrUnit1 FONTADDRUNIT1 [4] [3] [2] [1] OSDBGColor1 R/W [0] OSDFGColor1 R/W [0]
FONTADDRUNIT1: Defines the unit of font address and foreground and background colors of OSD1. OSDFGColor1 and OSDBGColor1 are meaningful only in one-byte character code mode. OSDFGColor1 <1:0> 00 01 10 11 OSDBGColor1 <3:2> Select foreground color of OSD1 (default value is 0) color 0 in LUT color 1 in LUT color 2 in LUT color 3 in LUT Select background color of OSD1 (default value is 0) Preliminary Version C1.1 52
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
AL700/701/710
00 01 10 11 FontAddrUnit1 <6:4> 000 001 010 011 100 101 110 111
color 0 in LUT color 1 in LUT color 2 in LUT color 3 in LUT Choose the font address unit of OSD1 (default value is 0) Font address is multiple of 2 3 bytes Font address is multiple of 2 4 bytes Font address is multiple of 2 5 bytes Font address is multiple of 2 6 bytes Font address is multiple of 2 7 bytes Font address is multiple of 2 8 bytes Font address is multiple of 2 9 bytes Font address is multiple of 210 bytes + (OSD1 Font RAM Start Address)
Font address = (Character Code) * (Font Address Unit) Character Code is the data retrieved from Context RAM. PixelDepth1 <7> 0 1 33h [7] [6] [5] Choose the depth of pixel (default value is 0) 1-bit mode 2-bit mode FONTLINESIZE1 [4] [3] [2] [1] Fontlinesize1 [7:0] FONTLINESIZE1: Defines the memory size for an OSD1 font line. Default value is 0. Fontlinesize1 34h [7] [6] [5] <7:0> memory size of a font line (unit: 1 byte) OSDHSTART1 [4] [3] [2] [1] OsdHStart1 [7:0] OSDHSTART1: Defines the horizontal start position of OSD1. Default value is 0. OsdHStart1 <7:0> OSD1 horizontal start position (unit: 8 pixels) R/W [0] R/W [0]
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
53
AL700/701/710
35h [7] [6] [5]
OSDVSTART1 [4] [3] [2] [1] OsdVStart1 [7:0]
R/W [0]
OSDVSTART1: Define the vertical start position of OSD1. Default value is 0. OsdVStart1 36h [7] [6] [5] <7:0> OSD1 vertical start position (unit: 4 lines) CONTEXTSTADDR1 [4] [3] [2] [1] ContextStAddr1 [7:0] CONTEXTSTADDR1: Defines the start address of OSD1 Context RAM. Default value is 0. ContextStAddr1 One byte mode Two byte mode <7:0> OSD1 Context RAM start address (Unit: 4 bytes/8 bytes for one-byte/two-byte mode respectively) R/W [0]
Start address of OSD1 Context RAM = ContextStAddr1 * 4 Start address of OSD1 Context RAM = ContextStAddr1 * 8
There is 1K Byte Context RAM built in AL700/701/710. 37h [7] [6] [5] RAMSTRIDE1 [4] [3] [2] [1] RamStride1 [7:0] RAMSTRIDE1: Defines how much Context RAM memory occupied by each OSD1 row text. Default value is 0. RamStride1 <7:0> Horizontal line stride of OSD1 Context RAM (Unit: 1 byte/2 bytes for one-byte/two-byte mode respectively) BMAPHSIZE1 [6] [5] [4] [3] [2] [1] BmapHSize1 [7:0] BMAPHSIZE1: Defines the horizontal size of OSD1 bitmap. Default value is 0. BMAPHSIZE1 = Actual horizontal size of OSD1 bitmap - 1 BmapHSize1 <7:0> OSD1 bitmap horizontal size (Unit: 1 OSD1 pixel) The difference of BMAPHTOTAL1 and BMAPHSIZE1 defines the extra gap between two adjacent characters shown on OSD1 screen. R/W [0] R/W [0]
38h [7]
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
54
AL700/701/710
39h [7] [6] [5]
BMAPHTOTAL1 [4] [3] [2] [1] BmapHTotal1 [7:0]
R/W [0]
BMAPHTOTAL1: Defines the total horizontal size of OSD1 bitmap. Default value is 0. BMAPHTOTAL1 = Actual total horizontal size of OSD1 bitmap - 1 BmapHTotal1 <7:0> OSD1 bitmap total horizontal size (Unit: 1 OSD1 pixel) BMAPVSIZE1 [6] [5] [4] [3] [2] [1] BmapVSize1 [7:0] BMAPVSIZE1: Defines the vertical size of OSD1 bitmap. Default value is 0. BMAPVSIZE1 = Actual vertical size of OSD1 bitmap - 1 BmapVSize1 <7:0> OSD1 bitmap vertical size (Unit: 1 OSD1 line) The difference of BMAPVTOTAL1 and BMAPVSIZE1defines the extra gap between two adjacent row texts shown on OSD1 screen. 3Bh [7] [6] [5] BMAPVTOTAL1 [4] [3] [2] [1] BmapVTotal1 [7:0] BMAPVTOTAL1: Defines the total vertical size of OSD1 bitmap. Default value is 0. BMAPVTOTAL1 = Actual total vertical size of OSD1 bitmap - 1 BmapVTotal1 3Ch [7] [6] [5] <7:0> OSD1 bitmap total vertical size (Unit: 1 OSD1 line) ICONHTOTAL1 [4] [3] [2] [1] IconHTotal1 [7:0] ICONHTOTAL1: Defines the total horizontal number of OSD1 icons. Default value is 0. ICONHTOTAL1 = Actual total horizontal number of OSD1 icons -1 IconHTotal1 <7:0> Total OSD1 horizontal icons (Unit: 1 icon) Total horizontal icon number defines how many character codes should be retrieved from internal OSD Context RAM and shown on OSD screen per OSD row text. R/W [0] R/W [0] R/W [0]
3Ah [7]
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
55
AL700/701/710
3Dh [7] [6] [5]
ICONVTOTAL1 [4] [3] [2] [1] IconVTotal1 [7:0]
R/W [0]
ICONVTOTAL1: Defines the total vertical number of OSD1 icons. Default value is 0. ICONVTOTAL1= Actual total vertical number of OSD1 icons -1 IconVTotal1 <7:0> Total OSD1 vertical icons (Unit: 1 icon) Total vertical icon number defines how many row texts can be shown on OSD screen. 8.2.8 OSD2 Control 40h [7] OSD2Blink_en [6] [5] OsdEn2 OSDCONTROL2 [4] Font2Byte2 [3] [2] [1] Vzoom2 R/W [0] Hzoom2
OSDCONTROL2: Defines the control configurations of OSD2 (On Screen Display 2) Hzoom2 <1:0> 00 01 10 11 Vzoom2 <3:2> 00 01 10 11 Font2Byte2 <4> 0 1 OsdEn2 <6:5> 00 01 10 Select the horizontal zoom factor of OSD 2 (default value is 0) OSD horizontal pixel size = 1 times of video pixel OSD horizontal pixel size = 2 times of video pixel OSD horizontal pixel size = 4 times of video pixel OSD horizontal pixel size = 8 times of video pixel Select the vertical zoom factor of OSD 2 (default value is 0) OSD vertical pixel size = 2 times of video pixel OSD vertical pixel size = 4 times of video pixel OSD vertical pixel size = 8 times of video pixel OSD vertical pixel size = 16 times of video pixel Select font character code mode (default value is 0) One-byte character code mode Two-byte character code mode OSD2 output selection (default value is 0) Disable OSD2 Enable OSD2 in monitor output Enable OSD2 in VCR output Preliminary Version C1.1 56
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
AL700/701/710
11 OSD2Blink_en <7> 0 1
Enable OSD2 in both monitor and VCR output Enable OSD2 blink function (default value is 0) Disable OSD2 blink Enable OSD2 blink
The blink attribute in the Context RAM will be disabled if the OSD2Blink_en is set to 0. 41h [7] [6] [5] FONTSTADDR2 [4] [3] [2] [1] FontStAddr2[7:0] FONTSTADDR2: Defines the start address of OSD2 Font RAM. Default value is 0. FontStAddr2 <7:0> OSD2 Font RAM start address (Unit: 8 bytes) OSD2 Font RAM start address = FontStAddr2 * 8 There is 4K Byte Font RAM built in AL700/701/710. 42h [7] PixelDepth2 [6] [5] FontAddrUnit2 FONTADDRUNIT2 [4] [3] [2] [1] OSDBGColor2 R/W [0] OSDFGColor2 R/W [0]
FONTADDRUNIT2: Defines the unit of font address and foreground and background colors of OSD2. OSDFGColor2 and OSDBGColor2 are meaningful only in one-byte character code mode. OSDFGColor2 <1:0> 00 01 10 11 OSDBGColor2 <3:2> 00 01 10 11 FontAddrUnit2 <6:4> 000 Select foreground color of OSD2 (default value is 0) color 0 in LUT color 1 in LUT color 2 in LUT color 3 in LUT Select background color of OSD2 (default value is 0) color 0 in LUT color 1 in LUT color 2 in LUT color 3 in LUT Choose the font address unit of OSD2 (default value is 0) Font address is multiple of 2 3 bytes Preliminary Version C1.1 57
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
AL700/701/710
001 010 011 100 101 110 111
Font address is multiple of 2 4 bytes Font address is multiple of 2 5 bytes Font address is multiple of 2 6 bytes Font address is multiple of 2 7 bytes Font address is multiple of 2 8 bytes Font address is multiple of 2 9 bytes Font address is multiple of 210 bytes + (OSD2 Font RAM Start Address)
Font address = (Character Code) * (Font Address Unit) Character Code is the data retrieved from Context RAM. PixelDepth2 <7> 0 1 43h [7] [6] [5] Choose the depth of pixel (default value is 0) 1-bit mode 2-bit mode FONTLINESIZE2 [4] [3] [2] [1] Fontlinesize2 [7:0] FONTLINESIZE2: Defines the memory size for an OSD2 font line. Default value is 0. Fontlinesize2 44h [7] [6] [5] <7:0> memory size of a font line (unit: 1 byte) OSDHSTART2 [4] [3] [2] [1] OsdHStart2 [7:0] OSDHSTART2: Defines the horizontal start position of OSD2. Default value is 0. OsdHStart2 45h [7] [6] [5] <7:0> OSD2 horizontal start position (unit: 8 pixels) OSDVSTART2 [4] [3] [2] [1] OsdVStart2 [7:0] OSDVSTART2: Define the vertical start position of OSD2. Default value is 0. OsdVStart2 <7:0> OSD2 vertical start position (unit: 4 lines) R/W [0] R/W [0] R/W [0]
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
58
AL700/701/710
46h [7] [6] [5]
CONTEXTSTADDR2 [4] [3] [2] [1] ContextStAddr2 [7:0]
R/W [0]
CONTEXTSTADDR2: Defines the start address of OSD2 Context RAM. Default value is 0. ContextStAddr2 One byte mode Two byte mode <7:0> OSD2 Context RAM start address (Unit: 4 bytes/8 bytes for one-byte/two-byte mode respectively)
Start address of OSD2 Context RAM = ContextStAddr1 * 4 Start address of OSD2 Context RAM = ContextStAddr1 * 8
There is 1K Byte Context RAM built in AL700/701/710. 47h [7] [6] [5] RAMSTRIDE2 [4] [3] [2] [1] RamStride2 [7:0] RAMSTRIDE2: Defines how much Context RAM memory occupied by each OSD2 row text. Default value is 0. RamStride2 <7:0> Horizontal line stride of OSD2 Context RAM (Unit: 1 byte/2 bytes for one-byte/two-byte mode respectively) BMAPHSIZE2 [6] [5] [4] [3] [2] [1] BmapHSize4 [7:0] BMAPHSIZE2: Defines the horizontal size of OSD2 bitmap. Default value is 0. BMAPHSIZE2 = Actual horizontal size of OSD2 bitmap - 1 BmapHSize2 <7:0> OSD2 bitmap horizontal size (Unit: 1 OSD2 pixel) The difference of BMAPHTOTAL2 and BMAPHSIZE2 defines the extra gap between two adjacent characters shown on OSD1 screen. 49h [7] [6] [5] BMAPHTOTAL2 [4] [3] [2] [1] BmapHTotal2 [7:0] BMAPHTOTAL2: Defines the total horizontal size of OSD2 bitmap. Default value is 0. BMAPHTOTAL2 = Actual total horizontal size of OSD2 bitmap - 1 R/W [0] R/W [0] R/W [0]
48h [7]
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
59
AL700/701/710
BmapHTotal2
<7:0>
OSD2 bitmap total horizontal size (Unit: 1 OSD2 pixel) BMAPVSIZE2 R/W [2] [1] [0]
4Ah [7] [6] [5]
[4]
[3]
BmapVSize2 [7:0] BMAPVSIZE2: Defines the vertical size of OSD2 bitmap. Default value is 0. BMAPVSIZE2 = Actual vertical size of OSD2 bitmap - 1 BmapVSize2 <7:0> OSD2 bitmap vertical size (Unit: 1 OSD2 line) The difference of BMAPVTOTAL2 and BMAPVSIZE2defines the extra gap between two adjacent row texts shown on OSD2 screen. 4Bh [7] [6] [5] BMAPVTOTAL2 [4] [3] [2] [1] BmapVTotal2 [7:0] BMAPVTOTAL2: Defines the total vertical size of OSD2 bitmap. Default value is 0. BMAPVTOTAL2 = Actual total vertical size of OSD2 bitmap - 1 BmapVTotal2 4Ch [7] [6] [5] <7:0> OSD2 bitmap total vertical size (Unit: 1 OSD2 line) ICONHTOTAL2 [4] [3] [2] [1] IconHTotal2 [7:0] ICONHTOTAL2: Defines the total horizontal number of OSD2 icons. Default value is 0. ICONHTOTAL2 = Actual total horizontal number of OSD2 icons -1 IconHTotal2 <7:0> Total OSD2 horizontal icons (Unit: 1 icon) Total horizontal icon number defines how many character codes should be retrieved from internal OSD Context RAM and shown on OSD screen per OSD row text. 4Dh [7] [6] [5] ICONVTOTAL2 [4] [3] [2] [1] IconVTotal2 [7:0] ICONVTOTAL2: Defines the total vertical number of OSD2 icons. Default value is 0. ICONVTOTAL2 = Actual total vertical number of OSD2 icons -1 IconVTotal2 <7:0> Total OSD2 vertical icons (Unit: 1 icon) Total vertical icon number defines how many row texts can be shown on OSD screen. (c)2001,2002-Copyright by AverLogic Technologies, Corp. Preliminary Version C1.1 60 R/W [0] R/W [0] R/W [0]
AL700/701/710
8.2.9 RAM Access 50h [7] 51h [7] 52h [7] OSDAdrst [6] [5] Reserved [6] [5] [6] [5] ADDRL [4] [3] [2] [1] Addr [7:0] ADDRM [4] [3] [2] [1] Addr [15:8] ADDRH [4] Target [3] [2] [1] Reserved W [0] Addr [17:16] W [0] W [0]
ADDRL, ADDRM, ADDRH: Defines the address of internal OSD Context RAM and Font RAM. Default address value is 0. Addr [7:0] Addr [15:8] Addr [17:16] Target <7:0> <7:0> <1:0> <4> 0 1 OSDAdrst <7> 0 1 53h [7] [6] [5] Address [7:0] Address [15:8] Address [17:16] Select the Context RAM or Font RAM (default value is 0) OSD Context RAM Font RAM Reset RAM address counter (default value is 0) Normal operation Reset RAM address counter to the initial value DATAPORT [4] [3] [2] [1] DATAPORT [7:0] DATAPORT: Defines the data port of internal OSD Context RAM and Font RAM. The data is written into the selected target RAM through this port. Default value is 0. DATAPORT <7:0> Written data of internal OSD Context RAM or Font RAM W [0]
Writing data to register #53h will automatically increase the RAM address defined in registers #50h, #51h, and #52h.
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
61
AL700/701/710
OSD Context RAM (write only): There is 1K-byte OSD Context RAM built in AL700/701/710. Therefore, there only need 10 bits to address the OSD Context RAM. 7 0 ADDRH (#52h) 654321 0 0 ADDRM (#51h) 7654321 Don't care 0 ADDRL (#50h) 7654321 OsdRamAddr [9:0] 0
For one byte data mode: 7 Reserved 6 DATAPORT (#53h) 5 4 3 2 Character Code [6:0] 1 0
For two byte data mode: 7 6 DATAPORT (#53h) 5 4 3 2 1 0 Character Code [7:0] BG Color Blink Character Code [10:8]
FG Color
(For byte 1) (For byte 2)
Character Code Blink <3> 0 1 BG Color <5:4> 00 01 10 11 FG Color <7:6> 00 01 10 11
Map to the font table to get the corresponding bit-map data Enable blinking function (default value is 0) Normal Enable Select background color from LUT (default value is 0) Select Color 0 in LUT Select Color 1 in LUT Select Color 2 in LUT Select Color 3 in LUT Select foreground color from LUT Select Color 0 in LUT Select Color 1 in LUT Select Color 2 in LUT Select Color 3 in LUT
Font RAM (write only): There is 4K-byte Font RAM built in AL700/701/710. Therefore, there only need 12 bits to address the Font RAM.
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
62
AL700/701/710
7 0
6
ADDRH (#52h) 54321 1
ADDRM (#51h) 07654321 Don't care
0
ADDRL (#50h) 7654321 FontAddr [11:0]
0
7
6
DATAPORT (#53h) 5 4 3 2 FontBMP
1
0
FontAddr = Character Code * FontAddrUnit + Font Line * Fontlinesize More detailed information please refers to the OSD function description paragraph. 8.2.10 Image Upload Setting 58h [7] [6] [5] Reserved UPIMGCTR [4] [3] [2] [1] R/W [0]
Burst_en UpImgRese Reserved Enable_UPI Read_Sel UpImgField
UPIMGCTR: Defines the control configurations of image upload UpImgField <0> 0 1 Read_Sel <1> 0 1 Enable_UPI <2> 0 1 UpImgReset <4> 0 1 Burst_en <5> 0 1 Choose what field to be uploaded (default value is 0) Upload ODD field Upload Even field Choose the mode of image upload (default value is 0) Upload color image Upload luminance color only Enable image upload (default value is 0) Disable Enable Reset internal image read counter (default value is 0) Normal operation Reset internal read counter for image uploading Select image read mode (default value is 0) Normal mode Burst mode
Internal image read counter will automatically increase when read UpImgYDP or UPImagCDP. To ensure image uploading correctly, the monitor output must be set to freeze mode and the internal image read counter must be reset before uploading an image.
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
63
AL700/701/710
59h [7] [6] [5]
UPIMGYDP [4] [3] [2] [1] UpImgYDP [7:0]
R [0]
UPIMGYDP: Defines the data reading port for image Y luminance. Default value is 0. UpImgYDP 5Ah [7] [6] [5] <7:0> Y luminance data of image UPIMGCDP [4] [3] [2] [1] UpImgCDP [7:0] UPIMGCDP: Defines the data reading port for image C chrominance. Default value is 0. UpImgCDP <7:0> C chrominance data of image R [0]
8.2.11 External Encoder Interface Setting 60h [7] 61h [7] [6] [5] [6] [5] HSYNCWIDTH [4] [3] [2] [1] HsyncWidth[7:0] HSYNCWIDTH [4] [3] [2] [1] Reserved R/W [0] HsyncWidth[9:8] R/W [0]
HSYNCWIDTH: Defines the HSYNC signal width. Default value is 0. HsyncWidth [7:0] HsyncWidth [9:8] 62h [7] [6] [5] <7:0> <1:0> Bits<7:0> of output HSYNC signal width (unit: pixel) Bits<9:8> of output HSYNC signal width (unit: pixel) VSYNCWIDTH [4] [3] [2] [1] VsyncWidth[7:0] VSYNCWIDTH: Defines the VSYNC signal width. Default value is 0. VsyncWidth <7:0> Output VSYNC signal width (unit: line) R/W [0]
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
64
AL700/701/710
8.2.12 Motion Detection 6Bh [7] [6] [5] addr_var MOTIONADDR: Defines the address of Mean and Variance. addr_mean <3:0> 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 addr_var <7:4> 0000 0001 0010 0011 0100 0101 0110 0111 Choose mean address (default value is 0) window [0] window [1] window [2] window [3] window [4] window [5] window [6] window [7] window [8] window [9] window [10] window [11] window [12] window [13] window [14] window [15] Choose variance address (default value is 0) window [0] window [1] window [2] window [3] window [4] window [5] window [6] window [7] Preliminary Version C1.1 65 MOTIONADDR [4] [3] [2] [1] addr_mean W [0]
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
AL700/701/710
1000 1001 1010 1011 1100 1101 1110 1111 6Ch [7] 6Dh [7] [6] [5] [6] [5]
window [8] window [9] window [10] window [11] window [12] window [13] window [14] window [15] MEANDATA [4] [3] [2] [1] data_mean [7:0] MEANDATA [4] [3] [2] [1] data_mean [15:8] R [0] R [0]
MEANDATA: Defines the mean data of selected mean address. Default value is 0. data_mean [7:0] data_mean [15:8] 6Eh [7] 6Fh [7] [6] [5] [6] [5] <7:0> <7:0> Low byte of mean data High byte of mean data VARIANCEDATA [4] [3] [2] [1] data_var [7:0] VARIANCEDATA [4] [3] [2] [1] data_var [15:8] VARIANCEDATA: Defines the variance data of selected variance address. Default value is 0. data_ var [7:0] data_ var [15:8] <7:0> <7:0> Low byte of variance data High byte of variance data R [0] R [0]
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
66
AL700/701/710
70h [7] 71h [7] [6] [5] [6] [5]
MEANTH0 [4] [3] [2] [1] th_mean0 [7:0] MEANTH0 [4] [3] [2] [1] th_mean0 [15:8]
W [0] W [0]
MEANTH0: Defines the threshold of mean data for window [3:0]. Default value is 0. th_mean0 [7:0] th_mean0 [15:8] 72h [7] 73h [7] [6] [5] [6] [5] <7:0> <7:0> Low byte of threshold of mean data for window [3:0] High byte of threshold of mean data for window [3:0] MEANTH1 [4] [3] [2] [1] th_mean1 [7:0] MEANTH1 [4] [3] [2] [1] th_mean1 [15:8] MEANTH1: Defines the threshold of mean data for window [7:4]. Default value is 0. th_mean1 [7:0] th_mean1 [15:8] 74h [7] 75h [7] [6] [5] [6] [5] <7:0> <7:0> Low byte of threshold of mean data for window [7:4] High byte of threshold of mean data for window [7:4] MEANTH2 [4] [3] [2] [1] th_mean2 [7:0] MEANTH2 [4] [3] [2] [1] th_mean2 [15:8] MEANTH2: Defines the threshold of mean data for window [11:8]. Default value is 0. th_mean2 [7:0] th_mean2 [15:8] <7:0> Low byte of threshold of mean data for window [11:8] <7:0> High byte of threshold of mean data for window [11:8] W [0] W [0] W [0] W [0]
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
67
AL700/701/710
76h [7] 77h [7] [6] [5] [6] [5]
MEANTH3 [4] [3] [2] [1] th_mean3 [7:0] MEANTH3 [4] [3] [2] [1] th_mean3 [15:8]
W [0] W [0]
MEANTH3: Defines the threshold of mean data for window [15:12]. Default value is 0. th_mean3 [7:0] th_mean3 [15:8] <7:0> <7:0> Low byte of threshold of mean data for window [15:12] High byte of threshold of mean data for window [15:12] VARIANCETH0 [6] [5] [4] [3] [2] [1] th_var0 [7:0] 79h [7] [6] [5] VARIANCETH0 [4] [3] [2] [1] th_var0 [15:8] VARIANCETH0: Defines the threshold of variance data for window [3:0]. Default value is 0. th_var0 [7:0] th_var0 [15:8] <7:0> <7:0> Low byte of threshold of variance data for window [3:0] High byte of threshold of variance data for window [3:0] VARIANCETH1 [6] [5] [4] [3] [2] [1] th_var1 [7:0] 7Bh [7] [6] [5] VARIANCETH1 [4] [3] [2] [1] th_var1 [15:8] VARIANCETH1: Defines the threshold of variance data for window [7:4]. Default value is 0. th_var1 [7:0] <7:0> Low byte of threshold of variance data for window [7:4] Preliminary Version C1.1 68 W [0] W [0] W [0] W [0]
78h [7]
7Ah [7]
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
AL700/701/710
th_var1 [15:8]
<7:0>
High byte of threshold of variance data for window [7:4] VARIANCETH2 W [2] [1] [0] W [2] [1] [0]
7Ch [7] 7Dh [7] [6] [5] [6] [5]
[4]
[3]
th_var2 [7:0] VARIANCETH2 [4] [3] th_var2 [15:8] VARIANCETH2: Defines the threshold of variance data for window [11:8]. Default value is 0. th_var2 [7:0] th_var2 [15:8] <7:0> <7:0> Low byte of threshold of variance data for window [11:8] High byte of threshold of variance data for window [11:8] VARIANCETH3 [6] [5] [4] [3] [2] [1] th_var3 [7:0] 7Fh [7] [6] [5] VARIANCETH3 [4] [3] [2] [1] th_var3 [15:8] VARIANCETH3: Defines the threshold of variance data for window [15:12]. Default value is 0. th_var3 [7:0] th_var3 [15:8] <7:0> <7:0> Low byte of threshold of variance data for window [15:12] High byte of threshold of variance data for window [15:12] W [0] W [0]
7Eh [7]
8.2.13 SDRAM Interface 80h [7] TRRD [6] TRP [5] TRCD DRAMCTL0 [4] [3] TRC [2] [1] TRAS R/W [0]
DRAMCTL0: Defines the control parameters of SDRAM. TRAS <1:0> Choose the latency of RAS (default value is 00) Preliminary Version C1.1 69
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
AL700/701/710
00 01 10 11 TRC <4:2> 000 001 010 011 100 101 110 111 TRCD <5> 0 1 TRP <6> 0 1 TRRD <7> 0 1 81h [7] Reserved [6] APON [5] Reserved
5 SDRAM input clocks 6 SDRAM input clocks 7 SDRAM input clocks 8 SDRAM input clocks Choose the latency of RC (default value is 000) 7 SDRAM input clocks 8 SDRAM input clocks 9 SDRAM input clocks 10 SDRAM input clocks 11 SDRAM input clocks 12 SDRAM input clocks 13 SDRAM input clocks 14 SDRAM input clocks Choose the latency of RCD (default value is 0) 2 SDRAM input clocks 3 SDRAM input clocks Choose the latency of RP (default value is 0) 2 SDRAM input clocks 3 SDRAM input clocks Choose the latency of RRD (default value is 0) 2 SDRAM input clocks 3 SDRAM input clocks DRAMCTL1 [4] [3] [2] TRW [1] TCL MEMCFG R/W [0] TWR
DRAMCTL1: Defines the control parameters of SDRAM. TWR <0> 0 1 TCL <1> 0 Choose the latency of WR (default value is 0) No latency 1 SDRAM input clock Choose the latency of CL (default value is 0) 2 SDRAM input clocks Preliminary Version C1.1 70
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
AL700/701/710
1 TRW <2> 0 1 MEMCFG <4:3> 00 01 10 11 APON <6> 0 1 82h [7] [6] [5]
3 SDRAM input clocks Choose the latency of RW (default value is 0) No latency 1 SDRAM input clock Select SDRAM type (default value is 0) 1M x 16-bit 4M x 16-bit Reserved Reserved Enable auto pre-charge (default value is 0) Disable Enable ENABLE_CTRL [4] [3] [2] [1] R/W [0]
enable_rfsh enable_fdr enable_qdr enable_cfw enable_cdw enable_ccw enable_cbw enable_caw
ENABLE_CTRL: Defines the control configurations of enable. enable_caw <0> 0 1 enable_cbw <1> 0 1 enable_ccw <2> 0 1 enable_cdw <3> 0 1 Enable FIFO write request of channel A in QUAD mode (default value is 0) Disable Enable Enable FIFO write request of channel B in QUAD mode (default value is 0) Disable Enable Enable FIFO write request of channel C in QUAD mode (default value is 0) Disable Enable Enable FIFO write request of channel D in QUAD mode (default value is 0) Disable Enable
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
71
AL700/701/710
enable_cfw
<4> 0 1
Enable FIFO write request of full channel in FULL mode (default value is 0) Disable Enable Enable FIFO read request of VCR output (default value is 0) Disable Enable Enable FIFO read request of monitor output (default value is 0) Disable Enable Enable SDRAM refresh (default value is 0) Disable Enable MIN_REFRESH R/W [2] [1] [0]
enable_qdr
<5> 0 1
enable_fdr
<6> 0 1
enable_rfsh
<7> 0 1
83h [7] [6] [5]
[4]
[3]
min_refresh [7:0] MIN_REFRESH: Defines minimum refresh times in one field period. Default value is 0. min_refresh <7:0> Minimum refresh times (Unit: 32) Only available while enable_rfsh is enabled 84h [7] [6] [5] Reserved CAW_LEVEL [4] [3] [2] [1] caw_level [5:0] R/W [0]
CAW_LEVEL: Defines the full level of FIFO of channel A in QUAD capture mode. Default value is 8. caw_level 85h [7] [6] [5] Reserved <5:0> Full level of FIFO of Channel A CBW_LEVEL [4] [3] [2] [1] cbw_level [5:0] R/W [0]
CBW_LEVEL: Defines the full level of FIFO of channel B in QUAD capture mode. Default value is 8. (c)2001,2002-Copyright by AverLogic Technologies, Corp. Preliminary Version C1.1 72
AL700/701/710
cbw_level 86h [7] [6]
<5:0>
Full level of FIFO of Channel B CCW_LEVEL R/W [2] [1] [0]
[5]
[4]
[3]
Reserved
ccw_level [5:0]
CCW_LEVEL: Defines the full level of FIFO of channel C in QUAD capture mode. Default value is 8. ccw_level 87h [7] [6] [5] Reserved <5:0> Full level of FIFO of Channel C CDW_LEVEL [4] [3] [2] [1] cdw_level [5:0] R/W [0]
CDW_LEVEL: Defines the full level of FIFO of channel D in QUAD capture mode. Default value is 8. cdw_level 88h [7] [6] [5] Reserved <5:0> Full level of FIFO of Channel D CFW_LEVEL [4] [3] [2] [1] cfw_level [5:0] R/W [0]
CFW_LEVEL: Defines the full level of FIFO in FULL video capture mode. Default value is 10h. cfw_level 89h [7] [6] [5] Reserved <5:0> Full level of FIFO QDR_LEVEL [4] [3] [2] [1] qdr_level [5:0] R/W [0]
QDR_LEVEL: Defines the empty level of FIFO of VCR output. Default value is 10h. qdr_level 8Ah [7] [6] [5] Reserved <5:0> Empty level of FIFO FDR_LEVEL [4] [3] [2] [1] fdr_level [5:0] R/W [0]
FDR_LEVEL: Defines the empty level of FIFO of monitor output. Default value is 10h. fdr_level <5:0> Empty level of FIFO
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
73
AL700/701/710
9 Electrical Characteristics
9.1 Absolute Maximum Ratings (Excessive ratings are harmful to the lifetime. Only for user guidelines, not tested.)
Parameter VDD VP IO TAMB Tstg TVSOL Supply Voltage Input Pin Voltage Output Current Ambient Op. Temperature Storage Temperature Vapor Phase Soldering Temperature (15 Sec.) 3.3V Rating -0.3 ~ +3.8 -0.3 ~ +(VDD+0.3) -20 ~ +20 0 ~ +85 -40 ~ +125 220 Unit V V mA C C C
9.2 Recommended Operating Conditions
Parameter Min. VDD VIH VIL TAMB Supply Voltage High Level Input Voltage Low Level Input Voltage Ambient Op. Temperature +3.0 0.7 VDD 0 0 3.3V Rating Typical +3.3 Max. +3.6 VDD 0.3 VDD +70 V V V C Unit
9.3 DC Characteristics (VDD = 3.3V, Vss=0V. TAMB = 0 to 70C; Some parameters are guaranteed by design only, not production tested)
Parameter Min. VIH VIL VOH VOL ILI ILO Hi-level Input Voltage Lo-level Input Voltage Hi-level Output Voltage Lo-level Output Voltage Input Leakage Current Output Leakage Current 0.7 VDD 0 2.4 -5 -5 3.3V Rating Typical Max. VDD 0.3 VDD VDD +0.4 +5 +5 V V V V A A Unit
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
74
AL700/701/710
9.4 AC Characteristics (VDD = 3.3V, Vss=0V, TAMB = 0 to 70C; Some parameters are guaranteed by design only, not production tested)
Parameter Min. Power Supply Current IDD Operating Current @27MHz Decoder Interface tCLK CLK tCLKr tCLKf tDIS tDIH Cycle time for VCLK_A, B, C, and D Duty Factor for CLK_A, B, C, and D (tCLKH / fCLK) Rising time for VCLK_A, B, C, and D Falling time for VCLK_A, B, C, and D Setup time for DI Hold time for DI 5 3 Encoder Interface (Output loading CL=15pF) tCK2 CK2 tr2 tf2 tPD2 tOH2 tCK tdCK tr2 tf2 tPD 2 times of cycle time for video output (VCLKX2) Duty Factor for VCLKX2 (tCK2H / tCK2) Rising time for VCLKX2 Falling time for VCLKX2 Propagation delay for DO in 8-bit output mode Hold time for DO in 8-bit output mode Cycle time for video output (VCLK) Clock delay for VCLK Rising time for VCLK Falling time for VCLK Propagation delay for DO in 16bit output mode 3 3 2 36 5 3 3 40 18 50 60 1.5 1.5 ns % ns ns ns ns ns ns ns ns ns 40 27 50 60 3 3 MHz % ns ns ns ns 220 mA 3.3V Rating Typical Max. Unit
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
75
AL700/701/710
Parameter Min. tOH Hold time for DO in 16-bit output mode 2
3.3V Rating Typical Max.
Unit ns
OSD Interface fCKOSD tCKOSD CKOSD tCKOSDr tCKOSDf tCKVBH tCKVBr tCKVBf Frequency for external OSD Cycle time for external OSD Duty Factor for OSD_CLK (tCKOSDH / tCKOSD) Rising time for OSD_CLK Falling time for OSD_CLK Pulse width high for OSD_VBLK Rising time for OSD_VBLK Falling time for OSD_VBLK 1/ fCKOSD 4 4 Serial Host Interface fSCL tSCLH tSCLL tSDAS tSDAH tSCLr tSCLf tSTARTH tSTOPS SCL (H_WRB) frequency Pulse width high for SCL Pulse width low for SCL Setup time for SDA (H_BUS7) Hold time for SDA Rising time for SCL and SDA Falling time for SCL and SDA Hold time for START condition Setup time for STOP condition 80 80 200 200 10 3 300 300 1 MHz ns ns ns ns ns ns ns ns 25 25 40 6.75 1/ fCKOSD 50 60 3 3 MHz ns % ns ns ns ns ns
Parallel Host Interface fWRB tWRBH tWRBL tBUSIS tBUSIH tWRBr tWRBf tHDRS H_WRB frequency Pulse width high for H_WRB Pulse width low for H_WRB Input setup time for H_BUS Input hold time for H_BUS Rising time for all signals Falling time for all signals Setup time for H_DENB, H_RDB 10 100 100 10 3 60 60 5 MHz ns ns ns ns ns ns ns
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
76
AL700/701/710
Parameter Min. tHDRH tBUSPD tBUSOH Hold time for H_DENB, H_RDB Output delay time for H_BUS Output hold time for H_BUS 5 Clock and Reset fXTI XTI fXTO fXTI_NTSC XTI_N fXTO_NTSC fXTI_PAL XTI_P fXTO_PAL fDMCLKI DMCLK fDMCLKO tRSTB XTI Duty Factor for XTI (tXTIH * fXTI) XTO XTI_NTSC Duty Factor for XTI_NTSC (tXTINH * fXTI_NTSC) XTO_NTSC XTI_PAL Duty Factor for XTI_PAL (tXTIPH* fXTI_PAL) XTO_PAL DMCLK_I Duty Factor for DMCLK_I (tDMCLKH* fDMCLKI) DMCLK_O Pulse width low for RSTB 108 40 40 40 40 3
3.3V Rating Typical Max.
Unit ns 40 ns ns
27 50 fXTI 28.6364 50 fXTI_NTSC 35.4690 50 fXTI_PAL 60 60 60
MHz % MHz MHz % MHz MHz % MHz MHz
50 fDMCLKI 1.32
60
% MHz ms
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
77
AL700/701/710
10 Timing Diagrams
tCLK VCLK_A VCLK_B VCLK_C VCLK_D
tCLKH
tCLKL tCLKf tDIS tCLKr
DI tDIH
AL700/701/710 656 or 601 8-bit Input Timing
tCK2
VCLKX2
tCK2H tCK2L tf2 tr2
tPD2
DO
tOH2
AL700/701/710 656 or 601 8-bit Output Timing
tCK2
VCLKX2
tCK2H tCK2L tf2 tr2
tCK
VCLK
tdCK tf tr tPD tOH
DO
AL700/701/710 601 16-bit Output Timing (c)2001,2002-Copyright by AverLogic Technologies, Corp. Preliminary Version C1.1 78
AL700/701/710
tCKOSD = 1/fCKOSD
OSD_CLK
tCKOSDH tCKOSDL tCKOSDf tCKOSDr
OSD Clock Output Timing
tCKVB = 1/fCKVB
OSD_VBLK
tCKVBH tCKVBL tCKVBr tCKVBf
OSD Video Blank Control Timing
fSCL
SCL(H_WRB)
tSCLH tSCLL tSCLf tSCLr
tSDAS
tSDAH
SDA(H_BUS7)
tSTARTH tSTOPS
Serial Host Interface Timing
fWRB
H_WRB
tWRBH tWRBL tWRBf tWRBr
tHDRH
H_DENB H_RDB
tHDRS tBUSPD tBUSOH
tBUSIS
tBUSIH
H_BUS
Parallel Host Interface Timing
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
79
AL700/701/710
fXTI
XTI
tXTIH tXTIL fXTO tPDXTO
XTO
XTI/XTO Clock Timing
fXTI_NTS
C
XTI_NTS C
tXTINH tXTINL
fXTO_NTSC tPDXTON
XTO_NTSC
XTI_NTSC/XTO_NTSC Clock Timing
fXTI_PAL
XTI_PAL
tXTIPH tXTIPL
fXTO_PAL tPDXTOP
XTO_PAL
XTI_PAL/XTO_PAL Clock Timing
fDMCLKI
DMCLK_I
tDMCLKH tDMCLK
L
fDMCLKO tPDDMCLK
DMCLK_O
DMCLK_I/DMCLK_O Clock Timing (c)2001,2002-Copyright by AverLogic Technologies, Corp. Preliminary Version C1.1 80
AL700/701/710
11 Mechanical Drawing-208 PIN PLASTICS PQFP
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
81
AL700/701/710
CONTACT INFORMATION
Averlogic Technologies Corp. 4F, No. 514, Sec. 2, Cheng Kung Rd., Nei-Hu Dist., Taipei, Taiwan Tel: +886 2-27915050 Fax: +886 2-27912132 E-mail: sales@averlogic.com.tw URL: http://www.averlogic.com.tw
Averlogic Technologies, Inc. 90 Great Oaks Blvd. #204, San Jose, CA 95119, U.S.A. Tel: 1 408 361-0400 Fax: 1 408 361-0404 E-mail: sales@averlogic.com URL: http://www.averlogic.com
(c)2001,2002-Copyright by AverLogic Technologies, Corp.
Preliminary Version C1.1
82